Alternating reference wordline scheme for fast dram

ABSTRACT

A fast DRAM memory uses ground-sensing as opposed to traditional Vdd/2 sensing. A selected DRAM cell connects to a bit-line true (BLT) or a bit-line complement (BLC). At the start of each cycle the BLT and BLC are restored to ground potential. A pair of alternating reference cells are provided for each bit-line. When a selected DRAM cell is connected either BLT or BLC the first reference cell in the pair is connected to the other bitline to provide a reference voltage to the other bitline which can be compared to the voltage provided by the selected DRAM cell. On a subsequent cycle using the same bitline the second reference cell in the pair is used. Thus it is not necessary to wait for the first reference cell to recharge prior to beginning the next cycle. Switching between the first and second reference cells in the pair alternates in this manner resulting in faster cycle time. The write-back of the reference cells can be hidden since an alternate cell is available for next cycle&#39;s reference bitline generation.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to dynamic random accessmemories (DRAMs) and, more particularly to a fast DRAM which uses analternating reference cells and a ground-sensing technique.

[0003] 2. Description of the Related Art

[0004] Dynamic random access memory (DRAM) performance is a well knownlimitation to computer system performance. Processor speeds are rapidlyoutpacing main memory performance, with both processor designers andsystem manufacturers developing higher performance memory subsystems inan effort to minimize performance limitations due to the slower DRAMdevices. Ideally, the memory performance would match or exceed processorperformance, i.e., a memory cycle time would be less than one processorclock cycle. This is almost never the case and, so, the memory is asystem bottleneck. While microprocessor speed has continued to increasealmost exponentially, DRAM performance lacks a correspondingimprovement. However, since DRAM memories continue to offer the highestdensity and lowest cost per bit they remain the most popular choice forcomputer system main memories.

[0005] By way of background, in their simplest form, a single DRAMmemory cell comprises a single transistor and a single capacitor.Depending on the convention used, if a charge is stored on the capacitorthe cell is said to store a 1-bit. If no charge is present, the cell issaid to store a 0-bit. Since the charge on the capacitor dissipates overtime, DRAM systems require additional overhead circuitry to periodicallyrefresh the charge on the capacitor. With modern lower voltage devicesit is difficult to distinguish the difference between 0 and a 1.Therefore, two bit lines are typically used for each bit with the firstin the bit line pair known as bit line true (BLT) and the other beingthe bit line complement (BLC). In this manner, it is actually thedifference between these two bit lines that determines the stored bitvalue.

[0006] The DRAM memory system is actually realized by incorporating manyof such DRAM cell pairs in an array. Any pair in the array isaddressable by row and column. The rows of the array are referred to a“word-lines” and the columns of the array are referred to as“bit-lines”. The bit lines occur in pairs, namely, bit-line true (BLT)and a bit-line complement (BLC). When a particular word-line isselected, all of the bit line pairs in that row are selected by a rowaddress strobe (RAS) signal. Thereafter, a particular bit-line pair isselected by the column address strobe (CAS) which identifies the desiredtrue and complement cell pair in the selected word-line to be read fromor written to. A sense amplifier is connected the true and complementbit-lines. The charge transferred from each memory cell to each bit-linein the pair is differentially amplified and latched by the senseamplifier thus reading out the bit.

[0007] Over the years, many improvements have been made to DRAM arrayarchitectures, address latching and decoding circuits, sensing schemes,data paths, and the like which have greatly increased the speed,reliability and performance of DRAM memories. In particular, engineershave minimized operational power and reduced noise by using what iscommonly referred to as half-Vdd (i.e. Vdd/2) sensing schemes. In aVdd/2 sensing scheme, the bit lines are precharged to a voltage of Vdd/2prior to reading. With Vdd/2 sensing when a particular cell is selectedthe charge stored on the memory cell capacitor will be shared with thebit line thus causing the voltage on the bit line to rise above or fallbelow Vdd/2. This difference is then sensed and amplified to read thebit. While providing benefits such as noise reduction, signaldevelopment is slowed due to the time required to precharge the bitlines and lower gain of the cell pass devices.

[0008] As is apparent from the above discussion, this type of DRAMsystem experiences what is commonly referred to as a destructive read.That is, when a particular cell is selected, the charge on the cellcapacitor is shared or discharged onto the bit line to be read. Hence,if a charge was stored on the capacitor indicating storage of a “1”,after the read the charge is no longer present. Thus, after a readoccurs, additional circuitry is required to rewrite the bit back intothe memory cell. Traditionally, this rewrite step was done in the samecycle as the read.

[0009] So called “fast” DRAM memories have been developed that do notrequire signal development and write-back of the cell within the sameDRAM cycle. The write-back of the cell occurs during a different cycle.As a result, by separating the read and write-back of the cell into twounique cycles the cycle time is decreased by roughly half of aconventional DRAM.

[0010] As shown in FIG. 1, there is shown a single column of a fast DRAMmemory array. Each memory location comprises a bit-line true (BLT) 10and a bit-line complement (BLC) 12 line, respectively, connected to asense amplifier shown in box 14. In addition to a sense amplifier, thebox 14 may also include additional circuitry such as isolation devicesand bit line precharge circuitry. A plurality of wordlines, labeledWORDLINE-0 to WORDLINE-n, share access to the BLT 10 and BLC 12. EachDRAM cell comprises a single capacitor 16 _(0-n) and a single FETtransistor 18 _(0-n) used to connect the capacitor to either the BLT 10or the BLC 12 when the appropriate wordline is selected. Also shown ineach DRAM cell is a resistor 20 _(0-n). However, this is a parasiticresistor inherent to the device and not an actual resistor purposelypositioned.

[0011] This “fast” DRAM may only be implemented with a half-VDD (Vdd/2)sensing scheme where the bit-lines are precharged to Vdd/2. As notedabove, this technique has several disadvantages including slow signaldevelopment time, limited low voltage functionality, slow sensingperformance from small overdrive, and small signal margins which resultsin a more sensitive design at lower voltages.

[0012] An alternative, perhaps more desirable approach would be to use aground-sensing scheme. In ground-sensing, each of the bit line pairs areprecharged or “restored” to ground potential prior to a read. Thereaftera reference cell is activated in tandem with the word line to place areference voltage on one of the bit-lines, either the BLT or BLC.

[0013] However, ground sensing will not work with this circuit. As anexample, if one were to try and read a 1-bit out from the BLT 10 onWORDLINE-0, using ground-sensing, both BLT 10 and BLC 12 would berestored to ground (i.e. brought to ground potential). WORDLINE-0 isbrought active and the charge stored on capacitor 16 ₀ would bedischarged to the BLT through transistor 18 ₀. Assuming ideal conditionsand thus neglecting the effects of parasitic resistance 20 ₀, thevoltage on BLT would be:$V_{BLT} = {V_{C}( \frac{C_{cell}}{C_{cell} + C_{BLT}} )}$

[0014] where

[0015] V_(c) is the voltage on the cell capacitor 16 ₀,

[0016] C_(cell) is the capacitance of capacitor 16 ₀, and

[0017] C_(BLT) is the capacitance of the BLT itself.

[0018] The sense amplifier 14 will be set and compares the voltages onBLT 10 and BLC 12. Based on the difference in voltages on BLT 10 and BLC12, the sense amplifier circuitry 14 will output a signal amplifying BLT10 to a full rail 1-bit signal and BLC 12 to a full rail 0-bit signalthus signifying that a 1-bit was stored in 16 ₀. However, as isapparent, ground sensing does not work well in the event a 0-bit isstored in 16 ₀ since in this case both BLT 10 and BLC 12 will have0-volts on them after reading a 0-bit. Thus, the sense amplifier hasnothing to compare leading to unpredictable results since there is noway to determine which of BLT 10 or BLC 12 should be amplified to railpotential.

SUMMARY OF TEE INVENTION

[0019] The present invention is directed to a fast DRAM memory whichuses ground-sensing as opposed to traditional Vdd/2 sensing. A selectedDRAM cell connects to a bit-line true (BLT) or a bit-line complement(BLC). A ground-sensing technique is used wherein at the start of eachcycle the BLT and BLC are restored to ground potential. A pair ofalternating reference cells are provided for each bit-line. When aselected DRAM cell is connected either BLT or BLC the first referencecell in the pair is connected to the other bitline to add a referencevoltage to the other bitline which can be compared to the voltageprovided by the selected DRAM cell. On a subsequent cycle using the samebitline the second reference cell in the pair is used. In this manner itis not necessary to wait for the first reference cell to recharge priorto beginning the next cycle. Switching between the first and secondreference cells in the pair alternates in this manner resulting infaster cycle time. The write-back of the reference cells can be hiddensince an alternate cell is available for next cycle's reference bitlinegeneration.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The foregoing and other objects, aspects and advantages will bebetter understood from the following detailed description of a preferredembodiment of the invention with reference to the drawings, in which:

[0021]FIG. 1 is a circuit diagram of a single column of a fast DRAMmemory array;

[0022]FIG. 2 is a is a circuit diagram of a single column of a fast DRAMmemory array using a single reference cell;

[0023]FIG. 3 is a waveform diagram of a single cycle of a DRAM cell readillustrating the wait time required when using a single reference cell;and

[0024]FIG. 4 is a circuit diagram of a single column of a fast DRAMmemory array using a pair of alternating reference cells.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

[0025] Referring now to the drawings, and more particularly to FIG. 2,there is shown a single column of a fast DRAM memory array using asingle reference cell similar to FIG. 1 with the addition of referencecells 22 and 24 associated with each of the BLT and BLC, respectively.If ground sensing is to be used in a fast DRAM application, thesereference cells should be used. Like elements in the various Figures arelabeled with like reference numerals and are therefore not discussedagain. Each reference cell includes a reference capacitor 26 which ischarged to a reference voltage VREF when a restore signal REQ₀₋₁activates a restore FET 28 ₀₋₁. VREF is selected as Vdd/2. Another FET30 ₀₋₁ is provided in each reference cell 22 and 24 to connect thereference cell to either the BLC or BLT when either RWL0 or RWL1 isactivated. Again, each of the capacitors 26 have parasitic resistancesassociated therewith collectively referenced as 32.

[0026] Following the same example as used above in FIG. 1, in order toread out a 1-bit from BLT 10 on WORDLINE-0, both BLT 10 and BLC 12 arerestored to ground (i.e. brought to ground potential) by bit linerestore circuitry in box 15. Ground restore circuitry, isolation devicesand sense amplifiers 15 are well known in the art and therefore detailsof these devices is omitted. REQ0 in the reference cell 24 is activatedto charge reference cell capacitor 26 ₀ to the potential on VREF throughtransistor 28 ₀. WORDLINE-0 is brought active and the charge stored oncapacitor 16 ₀ is discharged to BLT 10 through transistor 18 ₀, asbefore. Simultaneously with WORDLINE-0 being brought active thereference cell will be brought active thus discharging the charge storedin the reference cell 24 onto the complement bit-line BLC 12. Thevoltage on BLT 10 and BLC 12 is given by the equation:${V_{BLT} = {V_{C}( \frac{C_{cell}}{C_{cell} + C_{BLT}} )}},{V_{BLC} = {V_{ref}( \frac{C_{ref}}{C_{ref} + C_{BLC}} )}}$

[0027] where

[0028] V_(c) is the voltage on the cell capacitor 16 ₀ (Vdd),

[0029] C_(cell) is the capacitance of capacitor 16 ₀, and

[0030] C_(BLT) is the capacitance of the BLT line itself, and

[0031] where

[0032] V_(ref) is the voltage on the reference capacitor 26 ₀ (Vdd/2),

[0033] C_(ref) is the capacitance of capacitor 26 ₀, and

[0034] C_(BLC) is the capacitance of the BLC line itself.

[0035] In this case, assuming all capacitances are the same, V_(BLT)will be greater than V_(BLC) since V_(c) is greater than V_(ref). Thus,the sense amplifier will be set and will output a signal amplifying BLTto a full rail 1-bit signal and BLC to a full rail 0-bit signal thussignifying that a 1-bit was stored in 16 ₀.

[0036] Unlike the example shown in FIG. 1, using the reference cells 22and 24 will also allow a 0-bit to be read out of the fast DRAM usingground-sensing. In the case of a 0-bit is stored in cell 16 ₀, as seenin the above equations the voltage of BLT 10 will be 0-volts since V_(c)is 0-volts. However, BLC 12 will have a voltage on it due to thecontribution of V_(ref) provided by the reference cell 24. Thus, thesense amplifier can accurately compare the difference between V_(BTL)and V_(BTC) and output a full rail signals for BLT 10 and BLC 12indicating a 0-bit stored at cell 16 ₀.

[0037] However, although more robust, this scheme proves to be slow forthis application. The reason being that the reference cell (22 or 24)needs to be written back after being accessed in preparation for thenext cycle. As a result, the benefits of the “fast” DRAM architectureare severely impacted.

[0038]FIG. 3 shows a waveform diagram illustrating the problem. At thestart of a cycle, an equalization signal EQ is active thus causing BLT10 and BLC 12 to be restored to ground potential. The voltage on thereference node 26 ₀ (REF NODE) is set to V_(ref) (in this case, 0.6Volts). WORDLINE-0 and the reference wordline (RWL0) are then selectedcausing these signals to rise almost in unison. Once the WORDLINE-0 andRWLO are active, the sense amplifier 15 is set by signal SETP. Theactive WORDLINE-0 will cause cell 16 ₀ to begin to discharging onto BLTcausing the voltage on BLT to rise (assuming a 1-bit is stored at 16 ₀).Similarly, the active RWLO will cause the reference cell capacitor 26 ₀to discharge onto BLC 12. As shown, BLT 10 will raise higher than BLC12. The sense amplifier 15 will differentially amplify this differenceto read a 1-bit stored at cell 16 ₀. Immediately thereafter theequalization signal EQ goes active thus causing BLT 10 and BLC 12 to berestored to ground potential readying for the next cycle. The REQ0signal also goes active at this point in order to recharge the referencenode capacitor 26 ₀ with V_(ref). However, the problem lies in the factthat the next cycle cannot begin until the reference node is charged toat least 90% of V_(ref). This translates in practical terms to a waittime of approximately 1.4 ns in this example.

[0039] As shown in FIG. 4 in the preferred embodiment of the presentinvention, a pair of cells (22A-B and 24A-B) are used for each bit linerather than just one for each bit line as shown in FIG. 2. Again, likeitems are labeled with like reference numerals with the referencenumerals to the parasitic resistances being omitted to avoid clutterPreferably, the reference cells in each pair are the mirror image ofeach of other about VREF as shown. The alternating reference cells areused for each bitline to accomplish faster cycle time. As previouslydiscussed using a single reference cell, a next cycle cannot begin untilthe reference cell 26 is recharged to at least 90% of V_(ref) leading toundesired wait time. However, by using two alternating reference cellsfor each bit-line, if two adjacent wordlines are accessed back-to-back(e.g., WORDLINE-1 and WORDLINE-2), reference cell 22A would be assessedfor the first cycle by selecting wordline RWL1A simultaneously withWORDLINE-1 and reference cell 22B would be accessed for the second cycleby selecting RWL1B simultaneously with WORDLINE-2. A controller 40includes control circuitry for alternating between the reference cellpairs when adjacent wordlines are selected on adjacent cycles. While thesecond reference cell 22B is being used, the first reference cell can bewritten back. As a result, the second wordline activation can occurshortly after bitlines are fully precharged thus eliminating the waittime associated with using just one reference cell. In a similarfashion, reference cells 24A and 24B are used whenever accesses are madeto cells on bitline BLT 10.

[0040] While the invention has been described in terms of a singlepreferred embodiment, those skilled in the art will recognize that theinvention can be practiced with modification within the spirit and scopeof the appended claims.

I claim:
 1. A dynamic random access memory device, comprising: aplurality of wordlines; a plurality of memory cells for storing a 1-bitor a 0-bit; a pair of bitlines comprising a bitline true (BLT) and abitline complement (BLC), each said plurality of memory cells beingselectively connected to one of said BLT and BLC when a correspondingone of said plurality of wordlines is selected; a first pair ofreference cells connected to said BLT; a second pair of reference cellsconnected to said BLC; and a controller for alternating said first pairof reference cells when a memory cell is connected to said BLC onsuccessive cycles, and for alternating said second pair of referencecells when a memory cell is connected to said BLT on successive cycles.2. A dynamic random access memory device as recited in claim 1 whereinsaid controller restores each of said BLT and said BLC to groundpotential at a start of each cycle.
 3. A dynamic random access memorydevice as recited in claim 1 wherein each of said reference cellscomprise: a capacitor for storing a reference voltage; a first switchfor connecting said capacitor to a reference voltage line for chargingsaid capacitor; and a second switch for connecting said capacitor to oneof said BLT and said BLC for discharging said capacitor.
 4. A dynamicrandom access memory device as recited in claim 3 wherein said referencevoltage is Vdd/2.
 5. A dynamic random access memory device as recited inclaim 1 wherein each reference cell in said first and second referencecell pair is a mirror image of the other reference cell.
 6. A method ofcontrolling a fast dynamic random access memory (DRAM) withground-sensing, comprising the steps of: in a first cycle: restoring abitline pair to around potential; connecting a first DRAM cell to afirst bitline in said bitline pair causing said DRAM cell to share acharge stored therein with said first bitline; connecting a first in apair of reference cells to a second bitline causing said first referencecell to share a reference charge stored therein with said secondbitline; and sensing a voltage difference between said first and secondbitlines; in subsequent cycles: restoring said bitline pair to groundpotential; connecting another DRAM cell to said first bitline causingsaid another DRAM cell to share a charge stored therein with said firstbitline; alternately connecting said first and a second of saidreference cell pair to said second bitline causing said connectedreference cell share a reference charge stored therein with said secondbitline; and sensing a voltage difference between said first and secondbitlines.
 7. A method of controlling a fast dynamic random access memory(DRAM) with ground-sensing as recited in claim 6 further comprising thestep of: recharging one of said first and said second reference cellswhile the other is connected to said bitline.
 8. A method of controllinga fast dynamic random access memory (DRAM) with ground-sensing asrecited in claim 7 wherein said first and said second reference cells ischarged to Vdd/2.
 9. A dynamic random access memory device, comprising:a first pair of reference cells switchably connected to a bitline true(BLT); a second pair of reference cells switchably connected to a bitline complement (BLC), wherein first and second reference cells in saidfirst pair of reference cells are alternately connected to said BLT whena memory cell is connected to said BLC on successive cycles, and firstand second reference cells in said second pair of reference cells arealternately connected to said BLC when a memory cell is connected tosaid BLT on successive cycles.
 10. A dynamic random access memory deviceas recited in claim 9 wherein each of said BLT and said BLC are restoredto ground potential at a start of each cycle.
 11. A dynamic randomaccess memory device as recited in claim 9 wherein each of saidreference cells comprise: a capacitor for storing a reference voltage; afirst switch for connecting said capacitor to a reference voltage linefor charging said capacitor; and a second switch for connecting saidcapacitor to one of said BLT and said BLC for discharging saidcapacitor.
 12. A dynamic random access memory device as recited in claim11 wherein said reference voltage is Vdd/2.
 13. A dynamic random accessmemory device as recited in claim 9 wherein each reference cell in saidfirst aid second reference cell pair is a mirror image of the otherreference cell.
 14. A method of operating a fast dynamic random accessmemory (DRAM), comprising the steps of: providing a first pair ofreference cells to a bitline true (BLT); providing a second pair ofreference cells to a bit line complement (BLC); and alternatelyconnecting first and second reference cells in said first pair ofreference cells to said BLT when a memory cell is connected to said BLCon successive cycles, and alternately connecting first and secondreference cells in said second pair of reference cells to said BLC whena memory cell is connected to said BLT on successive cycles.
 15. Amethod of operating a fast dynamic random access memory (DRAM)as recitedin claim 14 further comprising the step of restoring each of said BLTand said BLC to ground potential at a start of each cycle.
 16. A methodof operating a fast dynamic random access memory (DRAM)as recited inclaim 14 further comprising the step of charging said reference cells insaid first and second pairs of reference cells to a reference voltage ofVdd/2.
 17. A method of operating a fast dynamic random access memory(DRAM)as recited in claim 14 further comprising the step of charging onereference cell in said first or second pair of reference cells whiledischarging the other reference cell in said pair of reference cells.18. A method of operating a fast dynamic random access memory (DRAM),comprising the steps of: providing a pair of reference cells to a firstbitline; and alternately connecting a first reference cell and a secondreference cell in said pair of reference cells to a second bitline whena memory cell is connected to said first bitline on successive cycles.19. A method of operating a fast dynamic random access memory (DRAM) asrecited in claim 18, further comprising the step of restoring saidbitline to ground potential at a start of each cycle.
 20. A method ofoperating a fast dynamic random access memory (DRAM)as recited in claim18 further comprising the step of charging said reference cells in saidpair of reference cells to a reference voltage of Vdd/2.